A dynamic verification library for Chisel.
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Updated
Nov 9, 2024 - Scala
A dynamic verification library for Chisel.
Coarse Grained Reconfigurable Arrays with Chisel3
A sequential signed FIR filter with ready/valid interfaces and buffered UART serialization, implemented in Chisel.
BCD to 7 Segment Decoder in Chisel3
A 16-bit accumulator processor in Chisel with masked instruction decoding, conditional branches, and an archived GCD execution trace.
We want to create FIRRTL as a Service. We mix Java and Scala for easily deploy
VLSI Subscalar Computation Implementation (Full Adder)
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